FPGA Engineer and Designer

UVM, RTL familiarity, SystemVerilog Key Responsibilities : Develop UVM-based verification environments Create and execute verification test plans Implement coverage-driven verification methodologies Collaborate with RTL developers to ensure design quality Develop automated test frameworks Document verification results and coverage metrics Requirements : Bachelor's degree in Electrical / Computer Engineering 7+ years experience in FPGA verification Expert knowledge of SystemVerilog and UVM Experience with simulation and verification tools Strong background in testbench development Current TS / / SCI clearance Desired Skills : Experience with formal verification methods Knowledge of networking protocols Experience with hardware security verification