Senior Physical Design Engineer
US Citizen or US Permanent Resident
Contract (6+ months with possible extensions)
Responsibilities :
- Architect system requirements
- Collaborate effectively with the full ASIC design implementation team with a Humble, Hungry and Smart attitude
- Leverage or enhance existing digital design flow and solve design and flow issues within Cadence Genus| Innovus | Tempus
- Plan budget, tools and team effort and champion project needs to ensure milestones and objectives are met
- Super user of industry standard Physical Design, Synthesis and Timing Analysis tools
- Accountable for physical design implementation of complex, low-power designs including physical-aware logic synthesis, DFT, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification
Skills / Experience :
BSEE / MSEE with 5+ years of related industry experience5+ years hands-on experience in high reliability, low power VLSI designs5+ years of experience with Cadence digital design tools (Genus, Innovus, Tempus)Basic proficiency with programming languages such as Perl, C and TCLExcellent understanding of reliability, test and power concepts & design tradeoffs requiredITAR compliance approval requiredKnowledge of MIPI, I2S, CAN protocols a plusSkilled with Verilog / VHDL RTL and able to modify for timing or power closureProduction-proven experience with Floor planning at Chip Level with Bus / Pin variables, Synthesis, Place and Route Optimization, Parasitic Extraction, Static Timing Analysis, Low Power Intent (UPF / CPF), Power Analysis, IR drop analysis, electromigration, Physical Verification and Sign OffPHYSICAL DESIGN GROUP on LinkedIn : https : / / www.linkedin.com / groups / 3626111 /