Digital Design EngineerSQL Pager LLC • San Jose, CA, United States
Digital Design Engineer
SQL Pager LLC • San Jose, CA, United States
job_description.job_card.30_days_ago
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job_description.job_card.job_descriptionMaster’s degree in Electrical Engineering or related field 3 years of industrial experience in ASIC Design Experience in micro-architecture and RTL design of complicated blocks Proficient in RTL design using HDL Familiar with design and verification tools (VCS, Verdi, DC, etc.) Hands on experience of ASIC design flow including RTL design, verification, Lint, CDC, LEC, Proficient scripting language in one of : Python, TCL, Shell, Perl Self-motivated team worker Hands on design experience in PCIe logical / link / transaction layers. Knowledge of PCIe / CXL Protocol Stacks, especially latest Generations Experiences in SerDes architectures Experiences in Digital Signal Processing Good debugging and problem-solving skills
Job Description :
- Define block level micro-architecture and write design specification
- RTL implementation of the specification while meeting power, area, timing constraints
- Work with Verification team to verify functionality
- Work with Backend team to go through ASIC flow to tape-out success
- Work with Firmware teams to develop APIs and help silicon bring up
- Post-silicon validation and debug
Minimal Qualifications :
logic synthesis, DFT, timing analysis, floor-planning, GLS, ECO, bring-up & lab debug
Preferred Qualifications :
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Digital Design Engineer • San Jose, CA, United States
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