Senior Design Verification Engineer
Job Description
As a Design Verification engineer on the ASIC team, you will ensure that the ASICs in our groundbreaking next‑generation firewall products meet or exceed industry‑leading requirements for features, performance, and reliability. You will define verification methodologies, architect test benches, write test plans, specify coverage, write tests, and debug across simulation, emulation, formal verification, and silicon validation.
Office‑Based Expectation
We expect office‑based employees to be in the office four days per week, with one day working from a location of their choice. This model promotes collaboration, informal problem‑solving, and the kinds of interactions that drive deep relationships and innovation.
Your Impact
Qualifications
Compensation Disclosure
The compensation offered for this position will depend on qualifications, experience, and work location. For candidates who receive an offer at the posted level, the starting base salary (for non‑sales roles) or base salary + commission target (for sales / commissioned roles) is expected to be between $235,000 – $260,000 per year. The offered compensation may also include restricted stock units and a bonus.
Our Commitment
We are committed to providing reasonable accommodations for all qualified individuals with a disability. If you require assistance or accommodation due to a disability or special need, please contact us at accommodations@paloaltonetworks.com.
EEO Statement
Palo Alto Networks is an equal‑opportunity employer. We celebrate diversity in our workplace, and all qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or other legally protected characteristics.
All your information will be kept confidential according to EEO guidelines.
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Asic Design Engineer • Santa Clara, CA, United States