Senior System Validation EngineerCypress HCM • San Jose, CA, US
Senior System Validation Engineer
Cypress HCM • San Jose, CA, US
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job_description.job_card.job_descriptionB.S. or M.S. in Computer Engineering, Electrical Engineering, or related field. 5+ years of experience in system validation, memory interfaces, or related semiconductor work. Must have expertise in high-speed interface concepts, including signal integrity and power integrity. Strong knowledge of processor / memory system architecture (DDR5 / DDR6 preferred). Experience with modeling / simulation tools for system-level validation. Hands-on experience with x86 computer / server platforms (Intel / AMD). Skilled with lab test and measurement equipment, troubleshooting, and debugging. Proficiency in scripting / programming (Python, C / C++); automation experience is a plus. Strong collaboration skills; works effectively with lab engineers, circuit designers, and validation teams. Experience with BIOS, firmware, DDR memory, or lab bench testing is preferable. $100,000-155,000+ depending on experience and location. Hybrid schedule (3 days onsite and 2 days remote), based in either San Jose, CA, or Johns Creek, GA
Job Description
Job Description
Senior System Validation Engineer
This exciting role will be responsible for validating high-speed memory buffer semiconductor products, developing automation scripts, and ensuring system compliance with performance specifications. The engineer will need to have deep experience with processor-memory interfaces (DDR5 / DDR6), high-speed signaling, and signal / power integrity to be successful in this role. They are headquartered in the San Jose, CA area, and this position can sit in either San Jose, CA, or Atlanta, GA area. The company is a silicon IP provider for the semiconductor manufacturing industry. If you are an individual who has expertise in validating memory buffer chips and loves to be hands-on and optimize processes, this role could be for you!
Responsibilities :
- Bring up and validate x86-based server systems with high-speed memory buffer products.
- Automate lab workflows : develop scripts for lab equipment control and data analysis.
- Support applications and design teams in debugging and resolving system-level issues.
- Collaborate on DDR system validation, including DDR topologies, protocols, and compliance.
- Work with design and validation teams to debug power delivery networks, signal / power noise, and other high-speed design challenges.
- Contribute to modeling, simulation, and system-level validation efforts.
Qualifications :
Salary Range :
Weekly Schedule :
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