FPGA Design Engineer – Data Center Accelerator Platforms

Find out more about this role by reading the information below, then apply to be considered.

Join a small, senior team at MemComputing that's rethinking how AI is computed in silicon. We're quietly building advanced AI hardware in stealth mode, and we're looking for engineers who want to help invent what comes after GPUs—while working closely with founders and architects on first-of-its-kind systems.

As our

• FPGA Design Engineer,
• you will develop high-performance accelerator subsystems for AI / LLM and HPC workloads. This role focuses on RTL design, PCIe, and memory subsystem development, and runtime integration using modern Xilinx frameworks (Vitis, XRT, Vivado). You will work across hardware architecture, host-FPGA interfaces, and performance optimization to deliver scalable accelerator solutions for data-center environments.
• Key Responsibilities
• Design accelerator data paths, control logic, and memory subsystems using Verilog / SystemVerilog, AXI / AXI-Stream, and HBM / DDR interfaces.
• Integrate PCIe Gen4 / Gen5 endpoints (XDMA / QDMA or custom IP) and collaborate with software engineers on Linux driver interaction, DMA flows, interrupts, and host-side APIs.
• Build FPGA platforms using Xilinx Vitis, XRT, Vitis HLS, and Alveo-style shell / user architectures; support host integration in C / C++ / Python.
• Optimize throughput, latency, bandwidth utilization, and multi-card scalability using Vitis Analyzer, ILA, PCIe debug tools, and performance profiling.
• Develop block- and subsystem-level simulations in QuestaSim, and perform synthesis, implementation, timing closure, and debug in Vivado.
• Required Qualifications
• BSEE / MSEE or equivalent in Electrical / Computer Engineering.
• 5+ years of hands-on FPGA design experience using Vivado targeting UltraScale or Versal platforms.
• Proficiency in SystemVerilog RTL design, simulation, and synthesis.
• Strong understanding of AXI-MM and related SoC interconnect architectures.
• Experience in hardware debug, timing closure, and large-scale FPGA design partitioning.
• Strong scripting skills in Tcl and Python.
• Familiarity with Linux driver-level interaction and FPGA system integration.
• Preferred / Nice-to-Have
• Design accelerator data paths, control logic, and memory subsystems using Verilog / SystemVerilog, AXI / AXI-Stream, and HBM / DDR interfaces.
• Integrate PCIe Gen4 / Gen5 endpoints (XDMA / QDMA or custom IP) and collaborate with software engineers on Linux driver interaction, DMA flows, interrupts, and host-side APIs.
• Build FPGA platforms using Xilinx Vitis, XRT, Vitis HLS, and Alveo-style shell / user architectures; support host integration in C / C++ / Python.
• Optimize throughput, latency, bandwidth utilization, and multi-card scalability using Vitis Analyzer, ILA, PCIe debug tools, and performance profiling.
• Develop block- and subsystem-level simulations in QuestaSim, and perform synthesis, implementation, timing closure, and debug in Vivado.
• Pay & Benefits
• Stock Options
• Up to 100% employer-paid
• Health, Dental, and Vision coverage for you and your family
• 401(k) through CalSavers
• Flexible schedule and high-autonomy environment
• Work alongside a senior technical team solving deep, meaningful problems
• MemComputing is an equal opportunity employer. xmcpwfu
• We welcome candidates of all backgrounds, identities, and experiences to apply.

Job Type : Full-time

Pay : $117,000.00 - $200,000.00 per year

Benefits :
• 401(k)
• Dental insurance
• Flexible schedule
• Health insurance
• Paid time off
• Vision insurance

Education :

• Bachelor's (Required)

Experience :

• FPGA Design : 5 years (Preferred)

Location :

• San Diego, CA 92122 (Preferred)

Ability to Commute :

• San Diego, CA 92122 (Required)

Ability to Relocate :

• San Diego, CA 92122 : Relocate before starting work (Required)

Work Location : In person