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Senior Manager, SOC Engineering

Senior Manager, SOC Engineering

SynopsysPlano, TX, US
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Senior Manager, Soc Engineering

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You are a seasoned design engineer with a passion for leading teams and driving complex projects to successful completion. With over 10 years of experience in designing and verifying ASIC / FPGA devices, you excel in applying modern design processes and flows for ASIC designs. Your strong technical background is complemented by your ability to collaborate effectively with cross-functional teams. You possess a detailed understanding of the ASIC design flow, from microarchitecture through RTL development, verification, synthesis, and timing closure. Your expertise in System Verilog RTL coding and review of complex designs, along with your experience with vendor tooling within an ASIC development flow, makes you an invaluable asset to any team. You thrive in dynamic environments, constantly seeking new challenges and opportunities to innovate.

You bring strategic vision and hands-on technical proficiency, inspiring and mentoring others while navigating complex design challenges. Your leadership style is inclusive and empowering, encouraging diverse perspectives to drive creativity and excellence. You are recognized for your ability to manage ambiguity, prioritize effectively, and deliver results that exceed expectations. Your commitment to continuous improvement and learning ensures that you and your team remain at the forefront of technological advancements. You value open communication, constructive feedback, and collaborative problem-solving, making you a trusted partner within Synopsys and with our customers.

Managing and leading a team of SoC / Subsystem Design Engineers across multiple customer engagements.

Collaborating with Synopsys customers to understand their requirements and define project scope and deliverables.

Mentoring and developing the design team, fostering growth for future assignments and technical excellence.

Applying modern ASIC design processes and flows, ensuring best practices in architecture and implementation.

Architecting designs from high-level requirements down to microarchitecture and partitioning tasks.

Partnering with cross-functional teams including verification, DFT, and physical design to ensure project success.

Implementing industry-standard methodologies for clocking, resets, metastability, and logical design for control / data paths.

Developing and reviewing System Verilog RTL code for complex system designs.

Driving the successful execution of full turnkey SoC designs from initial specification to silicon delivery.

Ensuring the delivery of high-quality, high-performance ASIC and FPGA devices for Synopsys customers.

Empowering customers to create groundbreaking products in high-performance computing, automotive, aerospace, defense, and more.

Advancing Synopsys' design methodologies and toolsets through continuous innovation and technical leadership.

Enhancing your team's capabilities, expertise, and effectiveness through strategic mentorship and coaching.

Supporting Synopsys' strategic objectives with your advanced technical solutions and leadership acumen.

Bachelor's or Master's Degree in Electrical or Computer Engineering.

10+ years of hands-on experience in designing and verifying ASIC / FPGA devices.

Strong proficiency in System Verilog RTL coding and design review for complex architectures.

Experience with vendor tools within an ASIC development flow (Simulators, LINT, CDC / RDC, Synthesis, STA).

Demonstrated ability to implement and debug complex protocols such as PCIe, Ethernet, UCIe.

An innovative and collaborative leader who fosters teamwork and inclusivity.

Excellent communicator, adept at conveying technical concepts to diverse audiences.

Strategic thinker with strong problem-solving capabilities and a drive for continuous improvement.

Resilient and adaptable, thriving in fast-paced, dynamic environments.

Confident decision-maker who inspires trust and motivates others to achieve their best.

You will join a dynamic and highly skilled team of ASIC and SoC engineers focused on delivering innovative solutions to industry-leading customers. The team embraces a culture of collaboration, knowledge sharing, and technical excellence, working together to solve complex engineering challenges and drive the success of Synopsys' projects. You'll have the opportunity to lead, mentor, and shape the future direction of the team while engaging with cross-functional experts in verification, DFT, and physical design.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Senior Engineering Manager • Plano, TX, US