Synopsys Flow Development & SOC implementation methodologies that will be deployed and used by our Synopsys customer Physical Design Implementation team members o Familiar with Synopsys Lynx a plus
RTL Hand-over experience a plus for RTL to GDS
Experience with top-level floorplanning, bump-maps, RDL IO Pad / Ring creation / verification, power grid creation / verification, hierarchal floorplanning / partitioning
Solid experience with full SOC clocking methodologies (H-Tree, Structure Clocking, MS CTS for Top / Blocks with push / down & bottoms up approaches)
Highly proficient with SDC STA constraints development driving back-end tools for blocks and full-chip through timing closure & sign-off o Ability to define sign-off requirements / margins based on Foundry technology requirements a plus
DFT experience with compression, scan, TDF, and MEMBIST a plus
Synopsys Formality for formal verification (RTL to Gate, Gate-to-Gate) & Formality ECO flows
Familiar with UPF flows & methodologies for multi-voltage power domains with turn on / turn off using UPF
Ansys Redhawk SC (For IR analysis for static, dynamic, & EMIR )
Experience in PD implementation / design closure on complex IP Sub-Systems such as PCIe, USB, MIPI, DDR, & HBM a plus
Experience with GlobalFoundries, TSMC, & Samsung technology nodes are a plus
Consultants should have a solid track record on execution delivering to high-quality standards for delivering to high quality tape-out The consultant needs to work well with cross-functional team members both within Synopsys and with our customers to meet their SOC development objectives. Warm Regards Neil Davis I Team Lead Agile Global Solutions, Inc ....."Empowering Enterprises" Donate Red || Save Blue || Spread Green 916-620-9993 Neil@agileglobalsolutions.com | www.agileglobal.com www.linkedin.com / in / neil-davis-l-i-o-n-616497a6
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