In this role you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture. You are responsible for developing verification methodology suitable for the IP ensuring a scalable and portable environment. You will get to develop verification environment including all the respective components such as stimulus checkers assertions trackers coverage. A mindset to break the design is highly you will develop verification plans for all features under your care execute verification plans including design bring-up DV environment bring- up regression enabling features and debug of the test failures. You will also learn to develop block IP and SoC level test-benches track and report DV progress using a variety of metrics including bugs and coverage. You will also be expected to make use of LLM and related technologies to achieve efficient execution and improved quality.
Key Skills
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Employment Type : Full Time
Experience : years
Vacancy : 1
Design Verification Engineer • Los Angeles, California, USA