RTL Engineer : System Verilog, UVM

Position : RTL Engineer

Location : Sunnyvale, CA || Hybrid

Fulltime

Role Overview

We are urgently seeking experienced RTL Engineers to join our team. The selected candidates will be responsible for developing and executing verification plans, building robust verification environments, and collaborating closely with design teams to ensure high-quality deliverables.

Responsibilities

• Plan : Develop comprehensive Core Verification Plans based on micro-architecture and design specifications.
• Develop : Architect and implement reusable, scalable verification environments using System Verilog / UVM.
• Test : Create and run constrained-random and directed tests to achieve high functional and code coverage.
• Debug : Analyze simulation results, root-cause complex failures, and work with design teams to resolve issues.
• Automate : Build and maintain automation scripts (Python / Perl) to enhance verification workflows and regression management.

Requirements

Added keywords for additional candidates.

HBM

Memory Controller

SoC

DRAM

TPU

ARM Cortex

ARM M7

There are three core expectations :

Thanks and Regards,

Manisha Dabral

Signature IT World Inc.