Lead Emulation Design Architect – High-Speed IP & AVIPCadence Design Systems • San Jose, CA, United States
Lead Emulation Design Architect – High-Speed IP & AVIP
Cadence Design Systems • San Jose, CA, United States
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A leading technology company is seeking a Senior Principal Emulation Design Engineer in San Jose. This role focuses on developing verification environments and requires strong experience with system-level designs and communication standards. Ideal candidates will possess a relevant degree and extensive experience in design. The position offers a competitive salary range from $154,000 to $286,000 along with numerous benefits.
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Design Lead • San Jose, CA, United States
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