Senior Staff RTL Design Engineer

This range is provided by AMD. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$191,040.00 / yr - $286,560.00 / yr

What you do at AMD

AMD's mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary.

When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

The Role

We are looking for a self‑motivated senior design engineer to be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry‑leading technologies to market. As a key contributor, you will focus on RTL design and validation of high‑speed interfaces such as chip‑to‑chip interconnect, both on system and on package, and highly configurable multi‑protocol PHYs. Continuous technical innovation to increase productivity, to heighten quality of results, and to foster career development is integral to the role.

The Person

You have a passion for digital design. You are a team player. You have strong analytical and problem‑solving skills. You are willing to learn and ready to take ownership of problems.

Key Responsibilities

Perform RTL design of the digital components.

Develop and validate timing constraints involving multiple clock domains while working with physical design to harden IP.

Help lead and mentor other engineers to achieve project goals and organizational growth.

Work with a functional (design) verification team to meet coverage and quality standards.

Analyze / fix lint and CDC / RDC errors of the components.

Guarantee quality / timely deliverables meeting project’s schedule.

Help to improve and automate design process.

Support post‑silicon product bring‑up / debug.

Preferred Experience

Strong experience in designing digital components for high performance, low power SOC / FPGA.

Design of digital circuits and components using Verilog / System Verilog.

Creating and maintenance of timing constraints for complex multi‑clock designs.

Debugging in digital and mixed‑signal simulation environment.

Power optimization of digital designs.

Multi‑clock domain designs.

Experience / knowledge of high‑speed SerDes / Physical layer is a plus.

Logic synthesis, timing closure, logical equivalence checking and ECOs.

Scripting languages such as Perl, Tcl, or Python.

Collaboration with verification team.

Excellent verbal and interpersonal communication skills.

Excellent technical communications. Ability to produce technical documentation.

Exhibit strong ownership of tasks and responsibilities.

Academic Credentials

Bachelor’s or Master’s degree in Electrical Engineering with relevant industry experience.

Location

San Jose, California

Benefits

Benefits offered are described : AMD benefits at a glance.

Equal Opportunity Employer

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal‑opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

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