DFT / DFD Design Verification Engineer, Chiplets (contractor)

DFT / DFD Design Verification Engineer, Chiplets (contractor)

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists has developed a high performance RISC-V CPU from scratch, and we share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Tenstorrent is seeking an experienced DFT / DFD Design Verification Engineer for a contract position to support the validation of cutting-edge test architectures in high-performance SoCs. In this role, you will verify Design-for-Test (DFT) and Design-for-Debug (DFD) logic—including JTAG, iJTAG, and internal scan architectures—ensuring robust manufacturability and post-silicon debuggability. You will work closely with DFT architects, RTL designers, and DV teams to develop and execute comprehensive verification plans using industry-standard tools and methodologies.

This is a fixed-term contract role and the candidates can be based in the US or Canada, and we are open to remote work.

Key Responsibilities :

• Define and execute verification plans for DFT / DFD features such as boundary scan, scan chains, and debug logic.
• Develop UVM-based or directed tests to validate IEEE 1149.x (JTAG), 1500 (iJTAG), and 1687 (IJTAG) compliant implementations.
• Verify integration and functionality of ICL (Instrument Connectivity Language) and PDL (Procedure Description Language) content for instrument and test control.
• Simulate and debug DFT / DFD RTL and gate-level designs using industry-standard simulators.
• Collaborate with DFT architecture and implementation teams to ensure functional correctness, performance, and alignment with manufacturability goals.
• Drive coverage closure, including code coverage and functional coverage, across all DFT / DFD blocks.
• Work with post-silicon validation and ATE teams to ensure test vector portability and alignment between simulation and silicon.

Experience & Qualifications :

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

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Equal Opportunity Employer information is available upon request. Tenstorrent does not discriminate on the basis of any protected characteristic. This description reflects the current requirements for the role and may be updated as needed.

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