Basic Qualifications
Requires a Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field. Also requires 2+ years of job-related experience or a Master's degree.
Clearance Requirements :
Department of Defense TS / SCI security clearance is preferred at time of hire. Candidates must be able to obtain a TS / SCI clearance within a reasonable amount of time from date of hire. Applicants selected will be subject to a Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, citizenship is required.
Responsibilities for this Position
Primary Job Qualifications :
We encourage you to apply if you have any of these preferred skills or experiences :
- In-depth experience using RTL simulation tools such as Siemens Mentor Graphics Questa or Modelsim tools or equivalent in a Linux Environment
- In-depth knowledge of System Verilog object oriented programming and the Universal Verification Methodology (UVM) Understands UVM Testbench Architectures Comfortable using and developing UVM agents , bus functional models Understands different types of coverage , usage of cover classes, cover points, etcExperience with predictive testbench components, functional coverage and assertions Experience with constrained random testingExperience with the Register Abstraction Layer
- Familiarity with requirements-based verification , requirement tracing, and developing requirement verification strategies etc
- Experience with scripting languages such as Linus shell scripts, TCL, Python
- Familiarity with using Formal Verification tools, code coverage, writing waivers etc
- Familiarity with the following are also helpfulQuesta Verification IP ( QVIP )Developing UVM testbenches for designs implemented in Xilinx devices with Xilinx IP and SoCs AXI protocols, PCIe, Space Wire, and Ethernet interfaces DSP functions and common signal processing componentsFamiliar with debugging FPGA / ASIC hardware and assisting with HW / SW integrationContinuous Integration features of GITLab
Duties and Tasks :
Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and / or FPGA (Field Programmable Gate Array) developmentsDetermines architecture, system simulation and detailed design approachDefines module interfaces and all aspects of device design and simulationCreates test and simulation plans that establish functional criteriaVerifies test results and analyzes performanceMay also review vendor capabilities and simulation toolsParticipates in the improvement of the ASIC / FPGA organizational processesSupports the generation of technical engineering products by using the appropriate standards, processes, procedures, and tools throughout the ASIC / FPGA development life cycleMay provide leadership and / or direction to lower level employeesIndependently determines approach to solutionsContributes to the completion of major programs and projectsPlans and executes project tasks for activities described aboveGeneral Knowledge, Skills and Abilities :
This candidate must have an ability to operate in a team environment and learn new skills to accomplish the verification goals.Proficient use and understanding of ASIC / FPGA engineering concepts, principles, and theoriesProficient in the principles and techniques of ASIC / FPGA design and the design processKeeps abreast of technology trendsProficient awareness of business objectives and Engineering’s role in achievingProficient in Microsoft Office applicationsProficient written and verbal communications skillsAbility to think creativelyAbility to multi-taskProficient skill in communicating issues, impacts, and corrective actionsRegular contact with senior levels of internal work groupsWorks under limited directionContact with project leaders and other professionals within the Engineering department and with project teams across the companySome contact with external customersWhat sets you apart :
Clear understanding of embedded micro-processing systems, FPGA Design and Verification using VHDL, and digital circuit analysis and designCollaborative, creative thinker with high proficiency in technical problem solvingTeam player with effective communication and presentation skillsExperience designing high speed interfaces and complex memory designsCommitment to ongoing professional development for yourself and othersOur Commitment to You :
An exciting career path with opportunities for continuous learning and development.Research oriented work, alongside award winning teams developing practical solutions for our nation’s securityFlexible schedules with every other Friday off work, if desired (9 / 80 schedule)Competitive benefits, including 401k matching, flex time off, paid parental leave, healthcare benefits, health & wellness programs, employee resource and social groups, and moreSee more atWorkplace Options :
This position is fully on-site or hybrid / flex, as mutually agreed.
While on-site, you will be a part of the Scottsdale, AZ team. Learn more at
Key Words : Verification, ASIC, FPGA, SystemVerilog, Verilog, Assertions (SVA), OVM, UVM, Digital Signal Processing (DSP), functional coverage, constrained random, formal verification, constrained random testing
LI-Hybrid
Target salary range : USD $111, - USD $123,;This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.