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Formal Verification Application Engineer

Formal Verification Application Engineer

SynopsysSunnyvale, CA, US
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Formal Verification Application Engineer

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

As an ideal candidate, you are a highly skilled and experienced Formal Verification engineer with a strong background in RTL design and a passion for ensuring the correctness and reliability of digital designs. You have a minimum of 5+ years of industry experience, with at least the last 4 years focused on formal techniques for verification. You possess knowledge of architectures of designs and digital logic, synthesis flow and formal checking. Your hands-on experience with HDLs such as Verilog or System Verilog and understanding of temporal logic assertions make you an ideal candidate for this role. You have worked on complex verification projects and have experience with formal verification tools like Jasper or VC-Formal. Your skills in Python, Perl, or Shell scripting are a plus. You are a team player with excellent communication skills, capable of mentoring junior engineers and collaborating with geographically diverse cross-functional teams. Your problem-solving abilities and attention to detail enable you to debug RTL designs effectively and identify causes of failure scenarios. You hold a Bachelor's or Master's degree in Computer Science or Electrical Engineering from a reputed engineering college.

What You'll Be Doing :

  • Providing pre / post-sales technical support for Synopsys VC Formal.
  • Analyzing customers' current verification methodologies and identifying areas for improvement.
  • Identifying key behaviors for verification of DUT and creating a formal verification plan.
  • Developing verification environments, including environment assumptions, assertions, and cover properties in the context of the verification plan.
  • Applying various formal verification techniques to prove the correctness of digital designs.
  • Debugging RTL to identify causes of failure scenarios.
  • Delivering presentations and demonstrations of Synopsys' formal verification technologies to potential and existing customers.
  • Collaborating with R&D teams to influence product development based on customer feedback and industry trends.

The Impact You Will Have :

  • Enhance the reliability and quality of our digital designs through rigorous formal verification.
  • Enhancing the adoption of Synopsys' VC Formal across the industry.
  • Strengthening Synopsys' market position as a leader in formal verification technology through exceptional customer support.
  • Influencing the development of future formal verification tools and methodologies based on real-world customer needs.
  • Contributing to the success of VC Formal through expert guidance and support.

    • What You'll Need :

  • BS in CS / EE with 4+ years of experience in formal verification.
  • In-depth knowledge of VLSI design flow and methodology, including HDL / HVL languages (SystemVerilog, Verilog, VHDL, SystemC).
  • Experience in front-end verification, including RTL / TB coding, formal, and debug.
  • Familiarity with property verification, equivalence checking and data path validation.
  • Proficiency in UNIX usage and scripting (shell, Python, tcl).

    • Who You Are :

  • Strong communicator with excellent verbal and written skills.
  • Collaborative team player who thrives in a dynamic environment.
  • Detail-oriented with strong analytical and problem-solving skills.
  • Innovative thinker with a passion for continuous learning and improvement.
  • Customer-focused with a commitment to providing exceptional support and service.

    • The Team You'll Be A Part Of :

    You will be a key member of the Customer Success Group, working with a talented team dedicated to supporting Synopsys' industry-leading formal verification platform. This team is focused on providing top-notch technical support and driving the adoption of advanced verification technologies to ensure the success of our customers' complex system-on-chip designs.

    We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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    Verification Engineer • Sunnyvale, CA, US