Senior FPGA Design Engineer (RTL & Vivado)

A leading engineering and R&D services firm in San Jose is seeking a professional with expertise in RTL design and Vivado Flow. The role involves collaborating with cross-functional teams, developing RTL methodologies, and performing testing with lab equipment. Candidates must have strong skills in debugging and protocol awareness, particularly with low-speed protocols like I²C and UART. This position offers a comprehensive benefits package, including healthcare and financial well-being programs.

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