Title : Silicon Design Package Engineer
Location : Santa Clara, CA (Day 1 onsite)
Duration : C2C
Job Description :
This role is highly specialized in semiconductor packaging design, requiring strong EDA tool proficiency and knowledge of advanced packaging technologies
Tools & Knowledge :
Mentor / Siemens and Cadence tools (especially for Package Layout Automation - PLA).
Technical Expertise :
Multi-layer package design experience.
Understanding of substrate manufacturing Design Rules and Assembly Rules.
Familiarity with SIPI (Signal Integrity & Power Integrity) Rules.
Flip-chip package design concepts
Design Engineer • Santa Clara, CA, United States