Senior ASIC Design Engineer

Senior ASIC Design Engineer

Location : On Site - San Jose, California, United States

Base pay range : $200,000.00 / yr - $230,000.00 / yr

Skills : ASIC Design, SystemVerilog, High Performance Compute, High-Speed Data Transport, PCIe / HBM

About the Technology Company / The Opportunity

Join a rapidly growing technology innovator dedicated to building next-generation infrastructure for AI advancement. This opportunity places you at the forefront of semiconductor and AI system design, empowering smarter devices and more sustainable data centers. As part of a world-class engineering team, you will contribute to the development of silicon solutions powering AI models, impacting the future of AI hardware and applications on a global scale.

Responsibilities

• Design high performance compute and high-speed data transport logic optimized for AI inference workloads.
• Integrate third-party and open source IP into complex chiplet architectures.
• Collaborate with verification engineers to develop verification strategies, drive coverage closure, and debug cross-functional design issues.
• Develop automation and methodologies to elevate productivity and product quality throughout the design process.
• Create comprehensive technical documentation, including microarchitecture specifications and integration guides.
• Contribute to architectural decisions that balance performance, power consumption, area, and development schedules.
• Work closely with physical design teams to ensure RTL supports timing closure, power targets, and manufacturability on advanced process nodes.

Must-Have Skills

Nice-to-Have Skills

Seniority level

Mid‑Senior level

Employment type

Full‑time

Job function

Engineering and Design

Industries

Technology, Information and Media and Semiconductor Manufacturing

Benefits

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