HW / SOC Physical Design Engineer : CTS & Timing Closure

A leading technology firm is seeking a Physical Design Engineer to join their team in San Diego, CA. The ideal candidate will have extensive experience in ASIC design, focusing on clock tree synthesis and verification. This role requires strong scripting skills and the ability to collaborate across functional teams to meet performance goals. A competitive salary range of $140,000 to $210,000 is offered, along with comprehensive benefits.

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