FPGA Verification Engineer

Job Description : Must-Have Skills UVM (Universal Verification Methodology) SystemVerilog RTL familiarity Key Responsibilities Develop UVM-based verification environments Create and execute comprehensive verification test plans Implement coverage-driven verification methodologies Collaborate closely with RTL developers to ensure design quality and functional completeness Develop automated test frameworks and workflows Document verification results, coverage metrics, and testbench performance Requirements Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field 7+ years of experience in FPGA verification Expert knowledge of SystemVerilog and UVM Experience with simulation and verification toolchains (e.g., Questa, VCS, Riviera, etc.) Strong background in testbench development and verification architecture Current TS / / SCI clearance Desired Skills Experience with formal verification methodologies Knowledge of networking protocols Experience with hardware security verification