Computer engineer serp_jobs.h1.location_city

Job Description

Job Description

Barbaricum is a rapidly growing government contractor providing leading-edge support to federal customers, with a particular focus on Defense and National Security mission sets. We leverage more than 17 years of support to stakeholders across the federal government, with established and growing capabilities across Intelligence, Analytics, Engineering, Mission Support, and Communications disciplines. Founded in 2008, our mission is to transform the way our customers approach constantly changing and complex problem sets by bringing to bear the latest in technology and the highest caliber of talent.

Headquartered in Washington, DC's historic Dupont Circle neighborhood, Barbaricum also has a corporate presence in Tampa, FL, Bedford, IN, and Dayton, OH, with team members across the United States and around the world. As a leader in our space, we partner with firms in the private sector, academic institutions, and industry associations with a goal of continually building our expertise and capabilities for the benefit of our employees and the customers we support. Through all of this, we have built a vibrant corporate culture diverse in expertise and perspectives with a focus on collaboration and innovation. Our teams are at the frontier of the Nation's most complex and rewarding challenges. Join our team.

Barbaricum is seeking a Computer Engineer to support Advanced Radars Test Capability Development for the Planar Antenna Array Assembly (PAAA). The ideal candidate will have a strong background in digital, hardware integration, and testing concepts within engineering fields like computer or electrical engineering. As a key contributor, you will focus on developing and maintaining digital system interfaces for signal processing and FPGA (VHDL) firmware, integrating hardware into test stations, and validating testing strategies. This role requires an individual with excellent communication skills to ensure seamless collaboration with the Task Manager, Integrated Project Team (IPT), and external vendors.

Responsibilities :

• Develop and maintain digital system interfaces for signal processing and FPGA (VHDL) firmware.
• Perform hardware integration into test stations using third-party hardware and firmware to meet testing requirements.
• Maintain testing strategies and digital communication structures in the technical drawing package.
• Integrate third-party C# software algorithms to validate test station performance.
• Provide weekly / bi-weekly status updates to the Task Manager and IPT, ensuring alignment with the Integrated Master Schedule (IMS).
• Participate in and brief during System Engineering Technical Review (SETR) events.
• Travel out-of-state to vendor locations as required.

Qualifications :

Preferred Qualifications :

This role requires onsite work at NSWC Crane for 3–4 days a week, with the possibility of remote work for the remaining days. Collaboration with cross-functional teams and external vendors is a key component of this position.

EEO Commitment

All qualified applicants will receive consideration for employment without regard to sex, race, ethnicity, age, national origin, citizenship, religion, physical or mental disability, medical condition, genetic information, pregnancy, family structure, marital status, ancestry, domestic partner status, sexual orientation, gender identity or expression, veteran or military status, or any other basis prohibited by law.